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MDT2030(CF)
1. General Description
This ROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve high speed, small size, the low power and high noise immunity. On chip memory includes 2K words EPROM, and 80 bytes static RAM. 2. Features The followings are some of the features on the hardware and software : Fully CMOS static design 8-bit data bus On chip EPROM size : 2.0 K words Internal RAM size : 80 bytes (73 general purpose registers, 7 special registers) 36 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.3 V ~ 6.0 V Operating frequency : 0 ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction Addressing modes include direct, indirect and relative addressing modes 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler On-chip RC oscillator based Watchdog Timer(WDT) 12 I/O pins with their own independent direction control
3. Applications
The application areas of this MDT2030 range from appliance motor control and high speed automotive to low power remote transmitters /receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral ... etc.
4. Pin Assignment DIP / SOP PA2 1 18 PA1 PA3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 2 3 4 5 6 7 8 9 17 16 15 14 13 12 11 10 PA0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4
Power-on Reset (POR),only available while PED is Disable
Power edge-detector Reset Sleep Mode for power saving 4 types of oscillator can be selected by programming option: RCLow cost RC oscillator LFXTLow frequency crystal oscillator XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator 4 oscillator start-up time can be selected by programming option: 150 s, 20 ms, 40 ms, 80 ms
SSOP PA2 1 20 PA1 PA3 RTCC /MCLR VSS VSS PB0 2 3 4 5 6 7 19 18 17 16 15 14 PA0 OSC1 OSC2 VDD VDD PB7
PB1 8 PB2 9 PB3 10
13 PB6 12 PB5 11 PB4 2007/8 Ver. 1.6
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P. 1
MDT2030(CF)
5. Block Diagram
S ta ck Two Le ve ls
EP RO M 2048X14
RAM 73X8 P ort A
P ort P A0~P A3 4 bits
11 bits 11 bits P rogra m Counte rs 14 bits Ins truction Re gis te r
S pe cia l Re gis te r P ort P B0~P B7 8 bits P ort B
OS C2 MCLR OS C1
D0~D7
Os cilla tor Circuit
Ins truction De code r
Control Circuit
Da ta 8-bit
P owe r on Re s e t P owe r Down Re s e t Working Re gis te r ALU S ta tus Re gis te r
8-bit Tim e r/Counte r
P re s ca le
WDT/OS T Tim e r
RTCC
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 2
2007/8
Ver. 1.6
MDT2030(CF)
6. Pin Function Description
Pin Name PA0~PA3 PB0~PB7 RTCC /MCLR OSC1 OSC2 Vdd Vss I/O I/O I/O I I I O Port A, TTL input level Port B, TTL input level Real Time Clock/Counter, Schmitt Trigger input levels Master Clear, Schmitt Trigger input levels Oscillator Input Oscillator Output Power supply Ground Function Description
7. Memory Map
(A) Register Map Address 00 01 02 03 04 05 06 07~1F 30~3F 50~5F 70~7F Description Indirect Addressing Register RTCC PC STATUS MSR Port A Port B Internal RAM, Memory bank 0 Internal RAM, Memory bank 1 Internal RAM, Memory bank 2 Internal RAM, memory bank 3
(1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1
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P. 3
2007/8
Ver. 1.6
MDT2030(CF)
(3) PC (Program Counter) : R2 Write PC, CALL --- always 0 JUMP --- from instruction word RTWI, RET --- from STACK
A10
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b6 b5 RTWI, RET --- from STACK
Write PC --- from ALU JUMP, CALL --- from instruction word RTWI, RET --- from STACK
(4) STATUS (Status register) : R3 Bit
0 1 2 3 4 6--5
Symbol
C HC Z PF TF page Carry bit Half Carry bit Zero bit
Function
Power loss Flag bit WDT Timer overflow Flag bit ROM page select bit : 00 : Page 0, 000H --- 1FFH 01 : Page 1, 200H --- 3FFH 10 : Page 2, 400H --- 5FFH 11 : Page 3, 600H --- 7FFH
7
----
General purpose bit
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P. 4
2007/8
Ver. 1.6
MDT2030(CF)
(5) MSR (Memory Bank Select Register) : R4 Memory Bank Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F
b7
b6
b5
b4
b3
b2
b1
b0
Read only "1" Indirect Addressing Mode (6) PORT A : R5 PA3~PA0, I/O Register (7) PORT B : R6 PB7~PB0, I/O Register (8) TMR (Time Mode Register) Bit Symbol Prescaler Value Function RTCC rate WDT rate
2--0
PS2--0
3
PSC
4
TCE
5
TCS
1:1 1:2 000 1:2 1:4 001 1:4 1:8 010 1:8 1 : 16 011 1 : 16 1 : 32 100 1 : 32 1 : 64 101 1 : 64 1 : 128 110 1 : 128 1 : 256 111 Prescaler assignment bit : 0 -- RTCC 1 -- Watchdog Timer RTCC signal Edge : 0 -- Increment on low-to-high transition on RTCC pin 1 -- Increment on high-to-low transition on RTCC pin RTCC signal set : 0 -- Internal instruction cycle clock 1 -- Transition on RTCC pin
(9) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is "write-only" "0", I/O pin in output mode; "1", I/O pin in input mode.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 5
2007/8
Ver. 1.6
MDT2030(CF)
(10) Configurable options for EPROM (Set by writer) : Oscillator Type RC Oscillator Oscillator Start-up Time 150 s,20ms,40ms,80ms 20 ms,40ms,80ms 20ms,40 ms,80ms 40 ms,80 ms
HFXT Oscillator XTAL Oscillator LFXT Oscillator
Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time
Power Edge Detect PED Disable PED Enable
Security state Security weak Disable Security Disable Security Enable
The default security state of EPROM is weak disable. Once the IC was set to enable or disable, it's forbidden to change. (B) Program Memory Address 000-7FF 7FF Program memory The starting address of power on, external reset or WDT time-out reset. Description
8. Reset Condition for all Registers
Register CPIO A CPIO B TMR IAR RTCC PC STATUS MSR Address 00h 01h 02h 03h 04h Power-On Reset 1111 1111 1111 1111 --11 1111 xxxx xxxx 1111 1111 0001 1xxx 100x xxxx /MCLR or WDT Reset 1111 1111 1111 1111 --11 1111 uuuu uuuu 1111 1111 000# #uuu 100u uuuu
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P. 6
2007/8
Ver. 1.6
MDT2030(CF)
Register PORT A PORT B Address 05h 06h Power-On Reset - - - - xxxx xxxx xxxx /MCLR or WDT Reset - - - - uuuu uuuu uuuu
Note : uunchanged, xunknown, - unimplemented, read as "0" #value depends on the condition of the following table
Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP
Status: bit 4 u 1 0 0
Status: bit 3 u 0 1 0
9. Instruction Set :
Instruction Code 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii Mnemonic Operands NOP CLRWT SLEEP TMODE RET CPIO R STWR R LDR R, t LDWI I SWAPR R, t INCR R, t INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t DECRSZ R, t ANDWR R, t ANDWI i IORWR R, t IORWI i No operation Clear Watchdog timer Sleep mode Load W to TMODE register Return Control I/O port register Store W to register Load register Load immediate to W Swap halves register Increment register Increment register, skip if zero Add W and register Subtract W from register Decrement register Decrement register, skip if zero AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Function Operating None 0WT 0WT, stop OSC WTMODE StackPC WCPIO r WR Rt IW [R(0~3) R(4~7)] t R + 1t R + 1t W + Rt R Wt or (R+/W+1t) R 1t R 1t R Wt i WW R Wt i WW TF, PF TF, PF None None None None Z None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z Status
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P. 7
2007/8
Ver. 1.6
MDT2030(CF)
Instruction Code 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 1000nn nnnnnnnn 1010nn nnnnnnnn 110000 nnnnnnnn 110001 iiiiiiii 11001n nnnnnnnn Mnemonic Operands XORWR R, t XORWI i COMR R, t RRR RLR CLRW CLRR BCR BSR R R, b R, b R, t R, t Function Exclu. OR W and register Exclu. OR W and immediate Complement register Rotate right register Rotate left register Clear working register Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Call subroutine Return, place immediate to W JUMP to address Operating R Wt i WW /Rt R(n) R(n-1), CR(7), R(0)C R(n)r(n+1), CR(0), R(7)C 0W 0R 0R(b) 1R(b) Skip if R(b)=0 Skip if R(b)=1 nPC, PC+1Stack nPC nPC, PC+1Stack StackPC,iW nPC Status Z Z Z C C Z Z None None None None None None None None None
BTSC R, b BTSS R, b LCALL n LJUMP n CALL RTWI JUMP n i n
Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive `' Exclusive `' Logic AND `' b t : : 0 1 R : C : HC : Z : / : x : i : n : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
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P. 8
2007/8
Ver. 1.6
MDT2030(CF)
10. Electrical Characteristics (Operating temperature at 25). Sym Description Condition Min 2.3 Vdd=5V Vdd=5V Vdd=5V Vdd=5V Vdd=5V Vdd=5V, IOL=20mA Vdd=5V, IOL=5mA Vdd=5V, IOH= -20mA Vdd=5V, IOH= -5mA Vdd2.3 ~ 6.0 V Vdd2.3 V Vdd3.0 V Vdd4.0 V Vdd5.0 V Vdd6.0 V 1.1 25.2 22.4 20.4 18.8 18.0 600 15 0.5 0.1 3.8 4.5 0.1 1 3 6 11 17 1.3 1.0 -0.6 -0.6 2.0 3.3 Typ Max 6.0 1.0 1.0 Vdd Vdd +/-1 Uni t V V V V V A V V V V A A A A A A V mS mS mS mS mS nS A Vdd-0.8 V v
Vdd Operating voltage VIL Input Low Voltage PA, PB RTCC, /MCLR VIH Input high Voltage PA, PB RTCC, /MCLR IIL Input leakage current VOL Output Low Voltage PA, PB VOH Output High Voltage PA, PB
Islp Sleep current (WDT disable) Islp Sleep current (WDT enable)
Vpr Power Edge-detector Reset Voltage Twdt The basic WDT time-out cycle Vdd2.3 V Vdd3.0 V time Vdd4.0 V Vdd5.0 V Vdd6.0 V TFLT /MCLR filter Icc Comparator Supply current (one comparator) Vref Input reference voltage Vdd5.0 V Vdd=5.0v Vdd=2.5v ~6.0 V
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 9
2007/8
Ver. 1.6
MDT2030(CF)
Sym Description Comparator Response time V-=Vdd/4, V+=V- 0.2v V-=Vdd/2, V+=V- 0.2v V-=Vdd3/4, V+=V- 0.2v V-=VDD-0.8,V+=V 0.2v Condition Vdd=5.0v , V- = Vref V+ = (PA0~PA3) Min Typ Max Uni t S S S S
---
8 8 8 8
11. Operating Current Temperature25 , the typical value as followings : 11.1 OSC TypeRC WDTEnable; @Vdd5.0 V PED=Disable Cext. (F) Rext. (Ohm) 4.7 K 10.0 K 3P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 20P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 100P 47.0 K 100.0 K 300.0 K 470.0 K Frequency (Hz) 11.2 M 5.94 M 1.40M 660 K 225 K 140 K 5.43 M 2.74 M 622 K 295 K 100 K 64 K 1.76 M 886 K 193 K 92 K 31 K 20 K Current (A) 1.2 mA 650 A 235 A 165 A 140 A 120 A 620 A 368 A 170 A 140 A 125 A 120 A 292 A 205A 145 A 130 A 130 A 125 A
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P. 10
2007/8
Ver. 1.6
MDT2030(CF)
Cext. (F) Rext. (Ohm) 4.7 K 10.0 K 300P 47.0 K 100.0 K 300.0 K 470.0 K PED=Disable Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 6.0 V Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.0 V PED=Disable Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.0 V 4M 150A 288A 510A 800A 1.3mA 10 M 320A 555A 910A 1.5mA 1.9mA 20 M X 925A 1.5mA 2.3mA 3.2mA Sleep 1.0 A 3 A 6 A 11 A 17 A 32 K (Ext100p) 7.0A 15.0A 35.0A 72.0A 130.0A 1M 50A 102A 215A 378A 650A 455 K (Ext50P) 2.6V@25.0 A 50A 88A 142A 220A 4M 120A 235A 405A 600A 855A 1M 40A 68A 120A 180A 260A 10 M 290A 500A 650A 1.3mA 1.6mA Sleep 1.0 A 1.0 A 1.0 A 1.0 A 1.0 A Frequency (Hz) 685 K 335 K 75 K 35 K 12 K 7K Current (A) 192 A 156 A 133 A 130 A 126 A 125 A
11.2 OSC TypeLF (OSC1&OSC2 External Cap about 10P); WDTDisable ;
11.3 OSC TypeXT (OSC1&OSC2 External Cap about 10P);
WDTEnable ;PED=Disable Sleep 1.0 A 3 A 6 A 11 A 17 A
11.4 OSC TypeHF (OSC1&OSC2 External Cap about 10P); WDTEnable ;
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 11
2007/8
Ver. 1.6
MDT2030(CF)
11.5 Power Edge-detector Reset Voltage (Not in Sleep Mode), @ Vdd5.0 V (PED:Enable) Vpr1.6~1.8 V Vpr Vdd (Power Supply)
PS. If PED_Enable then Internal Power_on_reset will be off 12. Port A and Port B Equivalent Circuit
D
I/O Control
Q I/O Control C Latch Q K B
D Write G Data O/P Latch Q B
Port I/O Pin
Data Bus D QB Data I/P Latch G TTL Input Level Input Resistor
Read
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 12
2007/8
Ver. 1.6
MDT2030(CF)
13. MCLRB and RTCC Input Equivalent Circuit
MCLRB
R1K
Schmitt Trigger
RTCC
R1K
Schmitt Trigger
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 13
2007/8
Ver. 1.6
MDT2030(CF)
14. External Capacitor Selection For Crystal Oscillator
@ Vdd5.0 V Osc. Type Resonator Freq. 20 MHz HF 10 MHz 4 MHz 10 MHz XT 4 MHz 1 MHz 1 MHz LF 455 K 32 K Capacity Range 10 pF ~ 50 pF 20 pF ~ 50 pF 10 pF ~ 30 pF 10 pF ~ 50 pF 10 pF ~ 50 pF 20 pF ~50 pF 20 pF ~ 30 pF 20 pF ~30 pF 20 pF ~30 pF
MDT2030
OSC1 OSC2
C1
C2
To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor are for reference only, but the higher capacitance also increases the start-up time.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 14
2007/8
Ver. 1.6

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